Performances of the Delay-Line Multiplier Circuit for Clock and Carrier Synchronization in Digital Satellite Communications

摘要: This paper is concerned with clock and carrier synchronization in digital satellite transmissions, using the delay-line multiplier circuit. For recovery from baseband signal, random data, a closed form formula derived which gives spectrum after multiplication, for any arbitrary pulse shape. contains spectral lines at frequency its harmonics, continuous part pattern noise. noise may be decomposed phase recovered clock, quadrature whose power density always zero frequency. The effect of Gaussian on channel taken into account to calculate signal-to-noise ratio as function classical parameter E/N_{o} . With modulated input carrier, signal output separated two parts: low that information bandpass around twice information, when possible. Spectrum are studied BPSK offset modulation.