Methods for gate-length biasing using annotation data
作者： Andrew B. Kahng , Puneet Gupta
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摘要: Methods for generating a biased layout making an integrated circuit are disclosed. One such method includes obtaining nominal defined by one or more cells, where each cell has transistor gate features with length. Then, annotated layout. The contains information describing gate-length biasing of the in cells A is produced modifying using from modifies length those identified
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