Influence of leakage reduction techniques on delay/leakage uncertainty
作者： Yuh-Fang Tsai , N. Vijaykrishnan , Yuan Xie , M.J. Irwin
关键词:
摘要: One of the main challenges for design in presence process variations is to cope with uncertainties delay and leakage power. In this paper, influence reduction techniques on delay/leakage uncertainty examined through Monte-Carlo analysis. The investigated paper include increasing gate length, stack forcing, body biasing, V/sub dd//V/sub th/ optimization. impact technology scaling temperature sensitivity are also evaluated. We investigate uncertainty-power-delay trade-off suggest designs targeting different requirements.
elsevier.com
acm.org
sci-hub.se 参考文章(12)
Y. Ye, S. Borkar, V. De, A new technique for standby leakage reduction in high-performance circuits symposium on vlsi circuits. pp. 40- 41 ,(1998) , 10.1109/VLSIC.1998.687996
Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De, Design and optimization of low voltage high performance dual threshold CMOS circuits design automation conference. pp. 489- 494 ,(1998) , 10.1145/277044.277179
A. Keshavarzi, K. Roy, C.F. Hawkins, Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions system level interconnect prediction. ,vol. 8, pp. 717- 723 ,(2000) , 10.1109/92.902266
T. Chen, S. Naffziger, Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation IEEE Transactions on Very Large Scale Integration Systems. ,vol. 11, pp. 888- 899 ,(2003) , 10.1109/TVLSI.2003.817120
Y.-F. Tsai, D. Duarte, N. Vijaykrishnan, M. J. Irwin, Implications of technology scaling on leakage reduction techniques Proceedings of the 40th conference on Design automation - DAC '03. pp. 187- 190 ,(2003) , 10.1145/775832.775880
Shekhar Borkar, Tanay Karnik, Siva Narendra, Jim Tschanz, Ali Keshavarzi, Vivek De, Parameter variations and impact on circuits and microarchitecture Proceedings of the 40th conference on Design automation - DAC '03. pp. 338- 342 ,(2003) , 10.1145/775832.775920
Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03. pp. 122- 127 ,(2003) , 10.1145/871506.871538
N. Sirisantana, L. Wei, K. Roy, High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness international conference on computer design. pp. 227- 232 ,(2000) , 10.1109/ICCD.2000.878290
S. Narendra, V. De, S. Borkar, D.A. Antoniadis, A.P. Chandrakasan, Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS IEEE Journal of Solid-state Circuits. ,vol. 39, pp. 501- 510 ,(2004) , 10.1109/JSSC.2003.821776
S.R. Nassif, Modeling and forecasting of manufacturing variations asia and south pacific design automation conference. pp. 145- 149 ,(2001) , 10.1109/ASPDAC.2001.913295