作者: Bhaskar Chatterjee , Manoj Sachdev , Steven Hsu , Ram Krishnamurthy , Shekhar Borkar
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摘要: This paper compares the effectiveness of different leakage control techniques in deep submicron (DSM) bulk CMOS technologies. Simulations show that 3-5/spl times/ increase I/sub OFF///spl mu/m per generation is offsetting savings switching energy obtained from technology scaling. We compare both transistor OFF/ reduction and ON/ degradation due to each technique for 130 nm-70 nm Our results indicate associated vs. delay tradeoffs depend on ratio energies a given technology. use our findings design 70 low power word line driver scheme 256 entry, 64-bit register file (R-F). As result, (total) drivers reduced by 3/spl (2.5/spl times/) RF up 35% (25%) respectively.