Methods for backplane interconnect testing

作者: Wuudiann Ke

DOI:

关键词:

摘要: A backplane testing method is provided in which test vectors are applied to individual circuit boards a system while remaining the disabled. The signals on all receivers observed during testing. connected bus multi-drop arrangement, so that can be addressed using slave interfaces. walking enable technique used systematically toggle of drivers boards. An intraboard for applying including an 0's vector, 1's and series generated from binary counting sequence. Backplane faults identified by comparing receiver expected response vectors.

参考文章(10)
Duane A. Delfosse, Robert J. Gallagher, Raymond P. Cronin, Bert Jepson, John R. Driscoll, John R. Kiely, Apparatus for testing circuit boards ,(1997)
L. Whetsel, A Proposed Method of Accessing 1149.1 in a Backplane Environment international test conference. pp. 206- 216 ,(1992) , 10.1109/TEST.1992.527821
EdwardP Hsieh, MauriceT McMahon, HenriD Schnurmann, Diagnostics of a board containing a plurality of hybrid electronic components Microelectronics Reliability. ,vol. 31, pp. 1060- ,(1989) , 10.1016/0026-2714(91)90199-H
F.W. Angelotti, W.A. Britson, K.T. Kaliszewski, S.M. Douskey, System level interconnect test in a tristate environment international test conference. pp. 45- 53 ,(1993) , 10.1109/TEST.1993.470719
Wuudiann Ke, Duy Le, N. Jarwala, A secure data transmission scheme for 1149.1 backplane test bus Proceedings of 1995 IEEE International Test Conference (ITC). pp. 789- 796 ,(1995) , 10.1109/TEST.1995.529910
Guntram K. Wolski, Peter A. Johnson, Built-in self-test tri-state architecture ,(1991)
Kenneth P. Parker, Kenneth E. Posse, Powered testing of mixed conventional/boundary-scan logic ,(1992)