Agile SMT-Based Mapping for CGRAs with Restricted Routing Networks

摘要: Coarse-grained reconfigurable architectures (CGRAs) are becoming popular accelerators for computationally intensive tasks. CGRAs offer the reconfigurability of an FPGA, but with larger configurable blocks which provide performance closer to ASICs. can achieve very high compute density if routing networks restricted; however, mapping using traditional annealing-based approaches does not perform well such architectures. This paper uses Satisfiability Modulo Theories (SMT) solvers rapidly map designs onto arbitrary CGRA fabrics. approach is sound, complete, and in many cases order magnitude faster than state-of-the-art constraint-based techniques integer linear programming (ILP). Additionally, we propose a functional duplication strategy that decreases pressure on network from high-fanout operations, leading significant improvements.