Method and apparatus for maintaining memory data integrity in an information handling system using cache coherency protocols
作者： Bernard Charles Drerup
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摘要: An information handling system includes a processor integrated circuit including multiple processors with respective cache memories. Enhanced coherency protocols achieve memory integrity in multi-processor environment. A bus controller manages interfaces to master devices and slave devices. In one embodiment, I/O device couple directly the while couples via controller. blocks partial responses that it receives from all except being included combined response sends over buses.
lens.org 参考文章(15)
Ravi Kumar Arimilli, Guy Lynn Guthrie, Leo James Clark, James Stephen Fields, Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop response ,(1999)
Blaine Douglas Gaither, Method and mechanism to use a cache to translate from a virtual bus to a physical bus ,(2000)
Clarence Rosser Ogilvie, Charles S. Woodruff, Transaction flow control mechanism for a bus bridge ,(2005)
David J. Harriman, Zohar Bogin, Zdzislaw A. Wirkus, Satish Acharya, Method and system for servicing cache line in response to partial cache line request ,(2000)
Stephen S. Pawlowski, D. Michael Bell, Peter D. MacWilliams, Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system ,(1996)
Maria M. Portuondo, Maurice Bizzarri, Willard Erickson, Stanford W. Crane, Backplane system having high-density electrical connectors ,(2003)
J.A. Reisner, T.S. Wailes, A cache coherency protocol for optically connected parallel computer systems high-performance computer architecture. pp. 222- 231 ,(1996) , 10.1109/HPCA.1996.501188
T. Terasawa, S. Ogura, K. Inoue, H. Amano, A cache coherency protocol for multiprocessor chip Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI). pp. 238- 247 ,(1995) , 10.1109/ICWSI.1995.515458
Hiroki Murata, Shigenori Shimizu, Multiprocessor cache system ,(1992)