Differential stage voltage offset trim circuitry

摘要: Differential stage voltage offset trim circuitry involves the use of one or more circuits, each which is dedicated to trimming particular source (Vos) error for a 'main' differential pair. One circuit may be Vos that arises due mismatch between main pairs' threshold voltages, and another beta values. Another can gamma pair transistors, respective circuits employed and/or transistors an active load driven by Several simultaneously reduce errors arise from several sources.