Scrambling/descrambling circuit
作者： Yuichi Kojima
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摘要: A scrambling/descrambling circuit that may be manufactured as a CMOS arrangement in LSI format and free of constraints on the degree generating polynomial involved. Scrambled (or descrambled) "m" bits data output by registers are multiplied multiplication circuits factor element α m polynomial. The input back to registers. scrambled supplied exclusive-OR gates for operation with data.
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