Spatially oversampled TDC with digital resolution enhancement
作者： Kameswaran Vengattaramane , Jonathan Borremans , Michiel Steyaert , Jan Craninckx
DOI: 10.1007/S10470-011-9669-7
关键词:
摘要: A digital resolution enhancement technique for time-to-digital converters (TDC) is proposed. This involves a simultaneous multi-channel measurement of time interval with low complexity TDC varying resolutions. The coarse outputs each converter are digitally post-processed to obtain an output whose precision much better than that the individual converters. Three post-processing algorithms proposed and their limitations in presence non-idealities analyzed. prototype system 8 channels implemented 90 nm CMOS. 40MS/s channel algorithmically combined over 2.2---3X measured improvement 4/6/8 modes, validating principle. chip occupies 0.3 mm2 draws up maximum 4 mA from 1.2 V supply.
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sci-hub.se 参考文章(16)
Sanjit K. K. Mitra, Digital Signal Processing : A Computer-Based Approach ,(1997)
Robert Bogdan Staszewski, Poras T. Balsara, All-digital frequency synthesizer in deep-submicron CMOS ,(2006)
V. Kratyuk, P. Hanumolu, K. Ok, K. Mayaram, U.-K. Moon, A Digital PLL with a Stochastic Time-to-Digital Converter symposium on vlsi circuits. pp. 31- 32 ,(2006) , 10.1109/VLSIC.2006.1705297
I. Nissinen, A. Mantyniemi, J. Kostamovaara, A CMOS time-to-digital converter based on a ring oscillator for a laser radar european solid-state circuits conference. pp. 469- 472 ,(2003) , 10.1109/ESSCIRC.2003.1257174
P. Dudek, S. Szczepanski, J.V. Hatfield, A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line IEEE Journal of Solid-state Circuits. ,vol. 35, pp. 240- 247 ,(2000) , 10.1109/4.823449
Matthew Z. Straayer, Michael H. Perrott, A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping IEEE Journal of Solid-state Circuits. ,vol. 44, pp. 1089- 1098 ,(2009) , 10.1109/JSSC.2009.2014709
Stephan Henzler, Siegmar Koeppe, Dominik Lorenz, Winfried Kamp, Ronald Kuenemund, Doris Schmitt-Landsiedel, A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion IEEE Journal of Solid-state Circuits. ,vol. 43, pp. 1666- 1676 ,(2008) , 10.1109/JSSC.2008.922712
J.-P. Jansson, A. Mantyniemi, J. Kostamovaara, A CMOS time-to-digital converter with better than 10 ps single-shot precision IEEE Journal of Solid-state Circuits. ,vol. 41, pp. 1286- 1296 ,(2006) , 10.1109/JSSC.2006.874281
Kameswaran Vengattaramane, Jonathan Borremans, Michiel Steyaert, Jan Craninckx, A gated ring oscillator based parallel-TDC system with digital resolution enhancement asian solid state circuits conference. pp. 57- 60 ,(2009) , 10.1109/ASSCC.2009.5357178
V Ramakrishnan, Poras T Balsara, None, A wide-range, high-resolution, compact, CMOS time to digital converter international conference on vlsi design. pp. 197- 202 ,(2006) , 10.1109/VLSID.2006.28