Multiprocessor computer system
作者： Asbjoern Smitt
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摘要: A multiprocessor computer system wherein memory bus means of separate central processing unit systems are interfaced to an intermemory communication network for transfer data between memories said systems. The communciation comprises a plurality preferably passive links being tapped connection link adapters interfacing number each link. may be different links. configurated allow direct any fraction without interfering with the units that controlled by access control means. includes configuration effective reconfigurate overall in event failure. reconfiguration switching fractions at least two sytems. Some directly addressable respective peripheral processor, one processors backing up others obtaining N+1 redundancy.
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