Memory controller with synchronous or asynchronous interface
作者： Frankie S. Shook , Kent S. Norgren , David E. Finlay
DOI:
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摘要: A common memory interfacing circuit and method for coupling a to either synchronous bus or an asynchronous bus. Synchronizing means are provided synchronizing request signals with local clock when the is coupled The interface responds from internal operation has been completed generates acknowledge signal send requesting To simplify circuit, protocol information exchange between system components made similar protocol.
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