作者: Fu-Chieh Hsu , Wing Yu Leung
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摘要: A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more masters. This includes lines segmented into sections linked together by programmable switches transceivers repeaters network. By: 1) use small block size (512K bit) for the memory modules; 2) identification register facilitate dynamic address mapping relatively easy incorporation global redundancy; 3) Use grid structure provide redundancy network; 4) narrow consisting 13 signal keep total area occupied small; 5) connected isolation defects; 6) special circuit asynchronous handshakes configuration; 7) control run-time reconfiguration; 8) spare local bus; 9) rows columns module redundancy, high defect tolerance obtained; 10) sense amplifiers already associated with arrays as speed (cache) memory.