A Fast Finite Field Multiplier
作者： Edgar Ferrer , Dorothy Bollman , Oscar Moreno
DOI: 10.1007/978-3-540-71431-6_22
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摘要: We present a method for implementing fast multiplier finite fields GF(2m) generated by irreducible trinomials of the form αm + αn 1. propose design based on Mastrovito which is described parallel/serial architecture that computes multiplication in m clock cycles using only bit-adders (XORs), bit-multipliers (ANDs), and shift registers. This approach exploits symmetries subexpression sharing matrices order to reduce number operations, hence computation time our FPGA implementation. According preliminary performance results, performs efficiently large has potential variety applications, such as cryptography, coding theory, reverse engineering problem genetic networks.
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