FPGA designs of parallel high performance GF(2 233 ) multipliers.

摘要: For many applications from the areas of cryptography and coding, finite field multiplication is most resource time consuming operation. We have designed optimized four high performance parallel GF (2) multipliers for an FPGA realization analyzed area complexities. One uses a new hybrid structure to implement Karatsuba algorithm. increasing performance, we make excessive use pipelining efficient control techniques modern state-of-the-art technology. As result have, our knowledge, first hardware subquadratic arithmetic currently fastest implementation 233 bit multipliers.