Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits

摘要: In this paper, a new low-swing wordline is proposed in order to reduce the oxide-tunneling leakage that important sub-65-nm SRAMs. This driver circuit turns off by using higher voltage than V SS , relaxing oxide stress of access transistor. By simulating 65-nm device Predictive Technology Model, scheme was verified be helpful reducing not only but also subthreshold leakage. The simulation indicates total reduced 10.3%, 18.5%, and 37.9% at temperatures 75 °C, 25 -25 respectively. read power 11.2%, 12.1 %, 12.4% ° C, write as much 31.0%, 33.4%, 34.8% A minimize delay penalty less 1% temperature °C. Similarly, with small overhead 2%