Automatic bias generation using pipeline instruction state coverage for biased random instruction generation

摘要: Biased random instruction generators are commonly used in architectural verification of microprocessors, with biases specified manually by designers. As the complexity processors grows, so does specifying biases. Automatic bias generation speeds up flow and may lead to better coverage potential design errors. In this work, we present a deterministic algorithm automatically generate that cover all pipeline states, where each state represents positions types instructions pipeline. Test programs generated from these can be for on-line testing field applications. The quality is evaluated using them test then simulating evaluating various metrics. Experimental results PowerPC ARM7 architectures show result higher error than provide key features.