A methodology to compute the statistical fault coverage of small delays due to opens
作者： Jose L. Garcia-Gervacio , Victor Champac
DOI: 10.1109/MWSCAS.2009.5235933
关键词:
摘要: Resistive opens in vias and interconnection lines have become an issue modern nanometer technologies. These defects may produce small delays which are difficult to detect pose a reliability problem. In this paper, statistical timing analysis framework is used analyze the detectability of due resistive considering process variations. A methodology estimate fault coverage these proposed. framework, variations considered, critical affecting performance test digital circuits. Inter-die intra-die considered. Using proposed methodology, producing evaluated for some ISCAS benchmark
computer.org
sci-hub.se 参考文章(12)
J.C.M. Li, Chao-Wen Tseng, E.J. McCluskey, Testing for resistive opens and stuck opens international test conference. pp. 1049- 1058 ,(2001) , 10.1109/TEST.2001.966731
Daniel Iparraguirre-Cardenas, Jose L. Garcia-Gervacio, Victor Champac, A design methodology for logic paths tolerant to local intra-die variations international symposium on circuits and systems. pp. 596- 599 ,(2008) , 10.1109/ISCAS.2008.4541488
Rajeshwary Tayade, Savithri Sundereswaran, Jacob Abraham, Small-Delay Defect Detection in the Presence of Process Variations international symposium on quality electronic design. pp. 711- 716 ,(2007) , 10.1109/ISQED.2007.145
R.R. Montanes, J.P. de Gyvez, P. Volf, Resistance characterization for weak open defects IEEE Design & Test of Computers. ,vol. 19, pp. 18- 26 ,(2002) , 10.1109/MDT.2002.1033788
Seung Hoon Choi, Bipul C. Paul, Kaushik Roy, Novel sizing algorithm for yield improvement under process variation in nanometer technology design automation conference. pp. 454- 459 ,(2004) , 10.1145/996566.996695
Aseem Agarwal, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda, Statistical delay computation considering spatial correlations asia and south pacific design automation conference. pp. 271- 276 ,(2003) , 10.1145/1119772.1119825
Kunhyuk Kang, B.C. Paul, K. Roy, Statistical Timing Analysis using Levelized Covariance Propagation design, automation, and test in europe. pp. 764- 769 ,(2005) , 10.1109/DATE.2005.279
Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D.M.H. Walker, A circuit level fault model for resistive opens and bridges vlsi test symposium. pp. 379- 384 ,(2003) , 10.1109/VTEST.2003.1197678
Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker, A Simulator of Small-Delay Faults Caused by Resistive-Open Defects european test symposium. pp. 113- 118 ,(2008) , 10.1109/ETS.2008.19
B. Kruseman, M. Heiligers, On test conditions for the detection of open defects design, automation, and test in europe. ,vol. 1, pp. 896- 901 ,(2006) , 10.1109/DATE.2006.243804