A design methodology for logic paths tolerant to local intra-die variations
作者： Daniel Iparraguirre-Cardenas , Jose L. Garcia-Gervacio , Victor Champac
DOI: 10.1109/ISCAS.2008.4541488
关键词:
摘要: Process variations have become a critical issue influencing the performance of nanometer digital circuits at gigascale integration; are classified in two types: inter-die and intra-die. Whereas affect deviation distribution lot chips, intra-die media distribution. The present work proposes new design methodology for designing logic paths tolerant to local variations. A library transistor structures with different degree delay variability is defined. Transistors from gates replaced these according selection criteria improve tolerance process variation on paths. Delay reduced expense circuit area. Results show significant reduction moderate increment area power consumption.
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