Study of the impact of variations of fabrication process on digital circuits

摘要: Designing digital circuits for sub-100nm bulk CMOS technology faces many challenges in terms of Process, Voltage, and Temperature variations. The focus has been on interdie variations that form the process In this work, we have focused two particular kinds variations- Inter-die NMOS to PMOS mismatch Intra-die local random mismatch. Neither had a noticeable effect industrial designs become cause worry only recently. source these lies basic is nature. Thus, their cannot be ameliorated without overhauling complete process. work academia mostly changes or architectural improvements. Our geared towards design improvements at gate path level. We looked phenomena behind using simulations observed how they affect different parameters design. was synchronous systems, i.e. clock distribution system highly impacted by proposed some methods optimization strategies make more robust. Most are exploitable within existing flows minimizes cost allows quick adoption industry. included voltage temperature put together comprehensive understanding. also verify basis our comparing against silicon test results. results helped shape policy handle designs.