Memory system segmented power supply and control

作者: Joseph T. Kennedy , Stephen R. Mooney , Robert M. Ellis

DOI:

关键词:

摘要: A memory device having cells supplied with a separate higher voltage power than the to logic, and lower state that entails removing from at least some of logic such refresh operations preserve contents continue take place, but interface is powered down reduce consumption.

参考文章(4)
Jim C. Tso, Vipul C. Patel, David R. Brown, DRAM power management with self-refresh ,(1992)
Hideto c o Mitsubishi Denki Kabushikki K. Hidaka, Semiconductor memory device with reduced current consumption in data hold mode ,(2000)