作者: Q.Z. Liu , B.A. Orner , L. Lanzerotti , M. Dahlstrom , W. Hodge
DOI: 10.1109/CSICS.2005.1531779
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摘要: With the advancement of fT/fMAX performance scaling SiGe HBTs breakdown voltage (BVCBO/BVCEO) reduces commensurately, causing design related concerns. It is important, therefore, that multiple fT/BVCEO devices be offered in RF technologies to meet varying needs communication products. Unlike GaAs technologies, BiCMOS are capable integrating various flavors HBT at a technology node. In this work, we investigate tradeoff fT-BVCEO for advanced by collector optimization schemes such as, subcollector dopant species and concentration, epilayer thickness, SIC other layout techniques.