作者: Marc Pastre , Maher Kayal , Hanspeter Schmid , Alexander Huber , Pascal Zwahlen
DOI: 10.1109/ESSCIRC.2009.5326033
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摘要: This paper presents a 5th-order ΔΣ capacitive accelerometer. The loop is implemented in mixed signal, the global filter having 2nd-order analog and 3rd-order digital part. system can be used with wide range of sensors, because mixed-signal front end programmable. ASIC developed comprises voltage-mode preamplifier, two parallel demodulators implementing CDS, 7-bit Flash ADC. latter drives filter, which configured for different sensor parameters order to ensure overall stability optimize noise performance. With low-noise MEMS sensor, achieves 19-bit DR 16-bit SNR, both over 300Hz bandwidth.