作者: S. Padmapriya , V. Lakshmi Prabha
DOI: 10.1016/J.MICPRO.2015.06.011
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摘要: Modern Digital Signal Processing systems require the reconfigurable FIR filters with low complexity architectures. This paper presents a novel architecture for power and area implementation of Finite Impulse Response (FIR) filter based on dual mode operation. The proposed technique operates in two modes. One is multiplier less which reduced another testable reversible operation to achieve power. Cadence Encounter synthesis results designed 75 taps savings up 37.97% reduction about 44.61% over conventional performance metric MSE, PSNR SMR values are found be 0.62, 50.24 80.8506 respectively.