Providing Extended Cache Replacement State Information
作者： Douglas M. Carmean , Andrew T. Forsyth , John C. Mejia , Eric Sprangle , Ramacharan Sundararaman
DOI:
关键词:
摘要: In an embodiment, a processor includes decode logic to receive and first memory access instruction store data in cache with replacement state indicator of level, send the decoded control logic. turn, is way set level metadata field responsive instruction. Other embodiments are described claimed.
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