Cache management device, system and method
作者： Jiao Xiao Kang
DOI:
关键词:
摘要: A cache memory is organized into a plurality of ways and address lines. In response to miss, the selects way based on first control variable indicating set second variables associated with line respective ways. Data miss written selected way. Second other are reset if all indicate was recently replaced. The Current values maintained in event hit.
lens.org 参考文章(13)
Michael A. Csoppenszky, Simplified least-recently-used entry replacement in associative cache memories and translation lookaside buffers ,(1996)
Nagi Nassief Mekhiel, Method and apparatus for reducing latency in a memory system ,(2001)
Tokuzo Kiyohara, Hazuki Okabayashi, Keisuke Kaneko, Takao Yamamoto, Ryuta Nakanishi, Tetsuya Tanaka, N-way set associative cache memory and control method thereof ,(2004)
Saneaki Tamaki, Shinichi Yoshioka, Susumu Narita, Ikuya Kawasaki, Processor with an addressable address translation buffer operative in associative and non-associative modes ,(1995)
Farnaz Mounes-Toussi, Method and apparatus for miss sequence cache block replacement utilizing a most recently used state ,(1997)
Douglas M. Carmean, Andrew T. Forsyth, John C. Mejia, Eric Sprangle, Ramacharan Sundararaman, Robert D. Cavin, Edward T. Grochowski, Providing Extended Cache Replacement State Information ,(2012)
Moinuddin K. Qureshi, David Thompson, Yale N. Patt, The V-Way Cache ACM SIGARCH Computer Architecture News. ,vol. 33, pp. 544- 555 ,(2005) , 10.1145/1080695.1070015
Keishi Chikamura, Hiroyuki Morishita, Ryuta Nakanishi, Tokuzou Kiyohara, Tetsuya Tanaka, Cache memory and cache memory control method ,(2004)
James D. Williams, Second chance replacement mechanism for a highly associative cache memory of a processor ,(2008)
Gordon Taylor Davis, Thomas Basilio Genduso, Performance of a cache by including a tag that stores an indication of a previously requested address by the processor not stored in the cache ,(2003)