Interconnect Optimization Considering Multiple Critical Paths

摘要: Interconnect optimization, including buffer insertion and Steiner tree construction, continues to be a pillar technology that largely determines overall chip performance. Buffer algorithms in published literature are mostly focused on optimizing only the most critical path. This is sensible approach for first order effect. As people strive squeeze out more performance post Moore's law era, timing of near paths worth considering as well. In this work, p-norm based Figure Of Merit (pFOM) proposed account both path timing. Accordingly, pFOM-driven method developed. Further, interaction with driven investigated. The techniques validated an industrial design flow results confirm their advantages.