Method of testing mosfet planar boards

摘要: A technique of testing a MOSFET planar board in which each the chips on can be electronically isolated for individual testing. In technology there are two off chip inverters between output logic blocks and pins. These preoff inverter inverter. NOR gate is formed by adding an additional input line to board, not tested driven logical ones application positive level this while no applied gates outputs tested. manner, all inputs at one or high level, test purposes brought low left accordance with pattern applied. Its reaction patterns monitored normal manner tester. Through utilization technique, same might number three thousand such that even though it remains equivalent new. defective without mechanically isolating breaking interconnections.