Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection

摘要: Design rules and test structure are used to implement machine designs thereby obviate during testing the need for mechanical probing of chip, multichip module, card or board at a higher level package. The design also provide means restricting size logic partitions on large logical structures facilitate pattern generation. A mechanism is available every chip be packaged drive data all outputs observe inputs, independent function performed by chip. control provided allow either perform its intended act as package test. It that built into will in place probes chip-in-place interchip wiring intent chips such each can "isolated" purposes through pins (or other contacts) containing chips. required "Level Sensitive Scan Design" (LSSD) discipline, rules, followed clock distribution network. Further, LSSD Rules which ensures capability scanning out SRLs (shift register latches) must satisfied total