Programmable logic device including a parallel input device for loading memory cells
作者： Lawrence C. Hung , Charles R. Erickson
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摘要: A device for configuring portions of an array memory cells a programmable logic comprises data register, plurality shift registers and control unit. The are loaded into out the register in parallel. Each outputs is coupled to serial input respective so can be shifted at same time. clock signal applied by unit serially loading load preferably simultaneously until store column transferred cells. each have outputs. different row then generates address transfer held
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