5-transistor memory cell with known state on power-up

摘要: A five transistor memory cell that can be reliably read and written from a single data line. The includes two inverters pass transistor. read/write circuitry an address supply voltage source which is maintained at first level during write second read, selected to reduce disturbance. circuit for precharging the line prior reading. state of continuously available output nodes control other even operation. Selective doping pull-up transistors in controls initial after powered up.