Programmable logic device with partially configurable memory cells and a method for configuration
作者： Lawrence C. Hung
DOI:
关键词: Physical address 、 Memory buffer register 、 Semiconductor memory 、 Memory map 、 Memory data register 、 Registered memory 、 Computer hardware 、 Flat memory model 、 Computer science 、 Memory address register
摘要: A field programmable gate array having memory cells that can be partially reconfigured comprises an of tiles logic blocks and routing structures, associated cells, a data register, address register configuration device. The is coupled to store in the by column. device preferably decoder control unit for receiving bit stream including skip command or write plus data. allows allowing each column selectively written skipped response inserted into stream. present invention also method reconfiguring steps of: retrieving packet from stream; determining whether command; if command, frame loading register; group cells; incrementing register.
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