Memory device comprising a memory cell and a selection transistor

作者: Seung Cheol Lee

DOI:

关键词:

摘要: A semiconductor device that includes a plurality of first conductive patterns stacked over substrate, dummy formed in the patterns, respectively, barrier each surrounding respective and partially interposed between second pattern located or under third pattern, wherein has greater thickness than patterns.

参考文章(10)
Yung-Tin Chen, Henry Chien, Xiying Costa, Johann Alsmeier, Chi-Ming Wang, Christopher Petti, Vertical nand and method of making thereof using sequential stack etching and landing pad ,(2014)
Chang-won Lee, Woong-Hee Sohn, Kyung-tae Jang, Myoung-Bum Lee, Ji-Youn Seo, Yong-chae Jung, Vertical memory devices and methods of manufacturing the same ,(2014)
Megumi Ishiduki, Masaru Kidoh, Ryota Katsumata, Hideaki Aochi, Yosuke Komori, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Masaru Kito, Non-volatile semiconductor storage device and method of manufacturing the same ,(2009)
Raul Adrian Cernea, Yung-Tin Chen, George Samachisa, 3D Non-Volatile Memory Having Low-Current Cells and Methods ,(2014)
Wonseok Cho, Changseok Kang, Jae-Joo Shim, Sung-Min Hwang, Hansoo Kim, Three dimensional semiconductor memory devices ,(2011)
Kwon Yong Hyun, Lee Ji Young, Seo Jun, Hwang Jae Seung, METHODS OF FORMING A PATTERN ,(2010)
Lee Chang Won, Lee Sun Woo, Lee Jeong Gil, Lee Sang Woo, NONVOLATILE MEMORY DEVICES AND METHOD FOR FABRICATING THE SAME ,(2010)
Tsuneo Uenaka, Kazuyuki Higashi, Makoto Wada, Naofumi Nakamura, Nonvolatile semiconductor memory device and method of manufacturing the same ,(2009)