作者: Richard Gerard Hofmann , Nader Amini , Terence Joseph Lohman , Patrick Maurice Bland , Bechara Fouad Boury
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摘要: A direct memory access (DMA) support mechanism is provided for use in a computer system which comprises (i) central processing unit (CPU) connected to by first bus, and second bus the CPU; (ii) host bridge connecting peripheral bus; (iii) an input/output (I/O) standard I/O having plurality of devices attached thereto; (v) arbitration logic functions mode arbitrating between competing grant wherein selected device granted bus. The DMA controller performing cycles on behalf device, enabling be performed over includes sideband signals directly with bridge, including information identifying size cycles.