引用次数
引用: 7,102
H-指数: 12
I10-指数 : 16
出版物: 34
Digital STDP synapse and LIF neuron-based neuromorphic system
Takeo Yasuda , Kohji Hosokawa , Masatoshi Ishii , Junka Okazawa
5
2015
Timing Sequence for Digital STDP Synapse and LIF Neuron-based Neuromorphic System
Takeo Yasuda , Kohji Hosokawa , Masatoshi Ishii , Junka Okazawa
2017
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation
Gary S. Ditlow , Robert K. Montoye , Salvatore N. Storino , Sherman M. Dance
international solid-state circuits conference 256 -258
25
2011
A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications
Hsiang-Lan Lung , Christopher P. Miller , Chia-Jung Chen , Scott C. Lewis
international memory workshop 1 -5
10
2016
A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing
John DeBrosse , Thomas Maffitt , Yutaka Nakamura , Guenole Jan
custom integrated circuits conference 1 -3
4
2015
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
Filipp Akopyan , Jun Sawada , Andrew Cassidy , Rodrigo Alvarez-Icaza
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34 ( 10) 1537 -1557
1,112
2015
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches
Leland Chang , Robert K. Montoye , Yutaka Nakamura , Kevin A. Batson
IEEE Journal of Solid-state Circuits 43 ( 4) 956 -963
327
2008
A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS
Leland Chang , Yutaka Nakamura , Robert K. Montoye , Jun Sawada
2007 IEEE Symposium on VLSI Circuits 252 -253
110
2007
Digitial STDP synapse and LIF neuron-based neuromorphic system
Takeo Yasuda , Kohji Hosokawa , Yutaka Nakamura , Junka Okazawa
Smpte Journal
2
2020
Hybrid static and dynamic sensing for memory arrays
Leland Chang , Robert K Montoye , Yutaka Nakamura ,
7
2010
A million spiking-neuron integrated circuit with a scalable communication network and interface
Paul A Merolla , John V Arthur , Rodrigo Alvarez-Icaza , Andrew S Cassidy
3,396
2014
Neural inference at the frontier of energy, space, and time
Dharmendra S Modha , Filipp Akopyan , Alexander Andreopoulos , Rathinakumar Appuswamy
Science 382 ( 6668) 329 -335
16
2023
IBM NorthPole Neural Inference Machine
Dharmendra S Modha , Filipp Akopyan , Alexander Andreopoulos , Rathinakumar Appuswamy
2023 IEEE Hot Chips 35 Symposium (HCS) 1 -58
2
2023
11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip
Andrew S Cassidy , John V Arthur , Filipp Akopyan , Alexander Andreopoulos
2024 IEEE International Solid-State Circuits Conference (ISSCC) 67 214 -215
2024
Time division multiplexed limited switch dynamic logic
Leland Chang , Robert K Montoye , Yutaka Nakamura
1
2016
Stacked, reconfigurable co-regulation of processing units for ultra-wide DVFS
Robert K Montoye , Kevin Tien , Yutaka Nakamura , Jeffrey Haskell Derby
2
2023
14
2009
Spin-torque transfer magneto-resistive memory architecture
John K DeBrosse , Yutaka Nakamura
12
2013
Ultra high-speed Nor-type LSDL/Domino combined address decoder
Robert Kevin Montoye , Yutaka Nakamura
12
2008
Dynamic semiconductor memory device and bit line precharge method therefor
Yutaka Nakamura , Toshio Sunaga
12
2005