3D memory with vertical bit lines and staircase word lines and vertical switches and methods thereof
作者： Raul Adrian Cernea , Roy E. Scheuerlein
DOI:
关键词: Offset (computer science) 、 Thin-film transistor 、 Engineering 、 Electrical engineering 、 Strongly coupled 、 Bit line 、 Coincident 、 3d memory 、 Bit field
摘要: A 3D memory with vertical local bit lines global has an in-line switch in the form of a thin film transistor (TFT) formed as structure, to line line. The TFT is implemented maximum current carried by strongly coupled select gate which must be fitted within space around Maximum thickness exclusively occupying along x-direction from both sides switches for odd and even row are staggered offset z-direction so that gates not coincident x-direction. switching further enhanced wrap-around gate.
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