Method for etching high-k dielectric using pulsed bias power
作者： Akiteru Ko , Alok Ranjan
DOI:
关键词: Layer (electronics) 、 Optoelectronics 、 Gate oxide 、 Plasma etching 、 Materials science 、 High-κ dielectric 、 Etching (microfabrication) 、 Substrate (electronics) 、 Analytical chemistry 、 Silicon 、 Gate dielectric
摘要: A method of patterning a gate stack on substrate is described. The includes preparing substrate, wherein the high-k layer and formed layer. further transferring pattern in to using pulsed bias plasma etching process, selecting process condition for achieve silicon recess having depth less than 2 nanometer (nm).
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