Power estimation considering statistical IC parametric variations

摘要: Statistical perturbations of process parameters may change propagation delays and alter the switching activity in circuit due to glitches. In this paper, problem estimating glitch/hazard power CMOS circuits is addressed. A probabilistic min/max delay model used, where variation between minimum maximum follow any given discrete probability distribution. The first part work considers glitching assuming fixed gate with instantaneous rise/fall times. Next, refined incorporate effects transition Experimental results on benchmark show that a significant amount dissipated hazards glitches hazardous dissipation sensitive variations delays.