Method of manufacturing a scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate
作者： Ching Dong Wang , Ching-Shi Jeng
DOI:
关键词: Gate oxide 、 EEPROM 、 Materials science 、 Communication channel 、 Metal gate 、 Flash (manufacturing) 、 Memory cell 、 Electrical engineering 、 Scalability
摘要: A scalable flash EEPROM cell having a semiconductor substrate with drain and source channel therebetween. select gate is positioned over portion of the insulated therefrom. floating spacer bottom surface second The has two side surfaces extending from surface. control includes first that adjacent surface,
lens.org 参考文章(12)
Kuo-Tung Sung, Tsong-Minn Hsieh, EPROM cell having a gate structure with dual side-wall spacers of differential composition ,(1998)
Ping Wang, Bing Yeh, A single transistor non-volatile electrically alterable semiconductor memory device ,(1992)
Hisakazu Iizuka, Method of operating a semiconductor memory circuit ,(1982)
Thomas Chang, Satyen Mukherjee, Single transistor electrically programmable memory device and method ,(1986)
Yueh Y. Ma, Kuo-Tung Chang, Flash eprom memory circuit having source side programming ,(1992)
Hideaki Arima, Natsuo Ajika, Electrically programmable non-volatie semiconductor memory device ,(1991)
Hui-Chen Chu, Wen-Cheng Chien, Multi-layer spacer technology for flash EEPROM ,(2000)
Ching-Shi Jenq, A scalable flash eeprom memory cell, method of manufacturing and operation thereof ,(1998)
Yoshimitsu Yamauchi, Nonvolatile memory, method of fabricating the same, and method of reading information from the same ,(1993)
Yoshimitsu Yamauchi, Non-volatile memory ,(1992)