Run-Time Power-Gating Techniques for Low-Power On-Chip Networks
作者： Hiroki Matsutani , Michihiro Koibuchi , Hiroshi Nakamura , Hideharu Amano
DOI: 10.1007/978-1-4419-6911-8_2
关键词: Power domains 、 Electronic engineering 、 Crossbar switch 、 Multiplexer 、 Low-power electronics 、 Power gating 、 Clock gating 、 AC power 、 Router 、 Engineering
摘要: Leakage power has already been consuming a considerable portion of the active in recent process technologies. In this chapter, we survey various gating techniques to reduce leakage on-chip routers. Then introduce run-time fine-grained power-gating router, which supply each router component (e.g., virtual-channel buffer, crossbar’s multiplexer, and output latch) can be individually controlled response applied workload. The with 35 micro-power domains is designed using commercial 65 nm evaluated terms area overhead, application performance, reduction.
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