Defect Oriented Testing for Analog/Mixed-Signal Devices

作者: N.R. Rai

DOI:

关键词: Digital electronicsFault (power engineering)SchematicReduction (complexity)Leakage (electronics)Electronic circuitIntegrated circuitEngineeringElectronic engineeringMixed-signal integrated circuit

摘要: Testing of Analog/Mixed-Signal (AMS) integrated circuits (ICs) has been one the most challenging topics in test technology community; this is because it very time consuming and hard to distinguish between pass fail as case for digital circuits. For some applications, such automotive industry, quality requirements AMS ICs can be severe zero Parts Per Million (PPM) level. This requires, addition optimizing time, also all possible defects IC. Bridges opens are common considered circuits; they analyzed Defect Oriented (DOT) flow order develop appropriate program. With high/severe new failure mechanisms have purposes. Investigating their impact on important especially PPM level application. thesis investigates effect dislocation an NXP IC which product, manufactured 140 nm technology. Dislocation cause leakage related failures while crossing a PN-junction device. It testing detect these defects. A schematic-based extraction methodology proposed extract based studying cross-sections different devices present Using extraction, defect list limited only 8% total active useful guiding analysis process reducing simulation effort considerably. These possess high resistive signature were simulated sets resistance values. was found that detectability decreases value increased. Test selection algorithms ‘greedy’ ‘unique detects first’ used obtain optimal set able defects, including The performance both terms reduction compared. obtained validating production data consisting 1.3 million dies. escaped diagnosed using fault dictionary approach. diagnosis results reveal current does not suffer from However, extra tests detecting kept advanced nodes future, if show up environment.

参考文章(29)
W. Maly, F. J. Ferguson, J. P. Shen, Systematic characterization of physical defects for fault analysis of MOS IC cells international test conference. pp. 390- 399 ,(1984)
S. Hamdioui, Testing multi-port memories: Theory and practice TU Delft, Delft University of Technology. ,(2001)
Z. Stanojevic, D.M.H. Walker, FedEx - a fast bridging fault extractor international test conference. pp. 696- 703 ,(2001) , 10.1109/TEST.2001.966690
Jerome, Post, Huffstater, Wodek, Travnicek, Williams, The effect of trench processing conditions on complementary bipolar analog devices with SOI/trench isolation bipolar/bicmos circuits and technology meeting. pp. 41- 44 ,(1993) , 10.1109/BIPOL.1993.617464
C.E. Stroud, J.M. Emmert, J.R. Bailey, K.S. Chhor, D. Nikolic, Bridging fault extraction from physical design data for manufacturing test development international test conference. pp. 760- 769 ,(2000) , 10.1109/TEST.2000.894272
Yizi Xing, Bram Kruseman, Bratislav Tasic, Camelia Hora, Jos Dohmen, Hamidreza Hashempour, Maikel van Beurden, Defect Oriented Testing for analog/mixed-signal devices 2011 IEEE International Test Conference. pp. 1- 10 ,(2011) , 10.1109/TEST.2011.6139127
Galiay, Crouzet, Vergniault, Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability IEEE Transactions on Computers. ,vol. 29, pp. 527- 531 ,(1980) , 10.1109/TC.1980.1675614