Scalable cache coherence for a network on a chip

摘要: Maintaining cache coherence in a System-on-a-Chip with both multiple coherent master IP cores (CCMs) and non-cache (NCMs). A plug-in manager (CM), logic agents, an interconnect are used for the SoC to provide scalable scheme that scales amount of CCMs SoC. The each includes at least one processor operatively coupled through CM stores data CCM. maintains responsive miss line on first caches, then broadcasts request instance stored corresponding cache. Each CCM its own NCM is configured issue communication transactions into non-coherent address spaces.