Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation
作者： Praveen K. Parvathala , Srinivas Patil , Irith Pomeranz
DOI: 10.1109/ATS.2007.18
关键词: Logic simulation 、 Real-time computing 、 Set (abstract data type) 、 Fault (power engineering) 、 Metric (mathematics) 、 Fault indicator 、 Fault coverage 、 Stuck-at fault 、 Algorithm 、 Automatic test pattern generation 、 Computer science
摘要: Functional test sequences were shown to detect defects that are not detected by structural tests. They also help in avoiding overtesting. However, fault simulation compute the stuck-at coverage of functional can be time consuming especially applications where a large number need evaluated and compared. To obtain fast yet accurate estimates coverages sequences, we describe metric based only on logic gate level circuit. The is set states circuit traverses under sequence. We define several versions suitable for different applications. present experimental results demonstrating effectiveness ranking their coverage.
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