作者: D. Defour , F. de Dinechin , J.-M. Muller
DOI: 10.1109/ACSSC.2002.1197049
关键词: Adder 、 Mathematics 、 Elementary function 、 Fixed-point arithmetic 、 Signal processing 、 Scheme (programming language) 、 Table (database) 、 Arithmetic
摘要: This paper presents a new scheme for the hardware evaluation of functions in fixed-point format, precisions up to 30 bits. yields an architecture made four look-up tables, multi-operand adder, and two small multipliers. method is evaluated compared with other published methods.