Stack gate with tip vertical memory and method for fabricating the same
作者： Ching-Nan Hsiao , Chi-Hui Lin , Ying-Cheng Chuang
DOI:
关键词: Fabrication 、 Gate oxide 、 Optoelectronics 、 Layer (electronics) 、 Materials science 、 Dielectric layer 、 Electrical engineering 、 Stack (abstract data type) 、 Gate dielectric 、 Flash memory 、 Trench
摘要: A stacked gate vertical flash memory and a fabrication method thereof. The comprises semiconductor substrate with trench, source conducting layer formed on the bottom of an insulating layer, dielectric sidewall spacer covering as floating gate, inter-gate spacer, control filled in trench.
google.de 参考文章(8)
Makoto Miyakawa, Yoshinori Sakaue, Donelli J. DiMaria, Claude L. Bertin, Method of fabricating three-dimensional direct-write EEPROM arrays ,(1995)
Jeng-Ping Lin, Jih-Chang Lien, Chi-Hui Lin, Pei-Ing Lee, Split gate flash memory cell ,(2003)
Da Soon Lee, Method for manufacturing a nonvolatile memory ,(2001)
Chi-Hui Lin, Chung-Lin Huang, Stacked gate flash memory device and method of fabricating the same ,(2003)
Chun Chiu Daniel Wong, Memory system having multiple programmable reference cells ,(1995)
Robin Lee, Flash memory structure and method of manufacture ,(1999)
Chi-Hui Lin, Split gate flash memory device and method of fabricating the same ,(2003)
Marius K. Orlowski, Ko-Min Chang, Process for forming an electrically programmable read-only memory cell ,(1994)