Fabrication of Si and Ge vertical nanowire for transistor applications

摘要: One–dimensional nanostructures, such as nanowhisker, nanorod, nanowire, nanopillar, nanocone, nanotip, nanoneedle, have attracted significant attentions in the past decades owing to their numerous applications electronics, photonics, energy conversion and storage, interfacing with biomolecules living cells. Such one–dimensional nanostructures are potential alternatives planar metal–oxide–semiconductor field–effect transistors (MOSFETs) owing, for example, unique electronic structure reduced carrier scattering caused by quantum confinement effects. Yet whether nanowire field effect (NWFETs) can indeed outperform counterparts is still unclear [1]. Three–dimensional integration combination of different material systems central themes electronics research. The manufacturing nanostructured devices relies on either bottom–up approaches synthesis or growth process top–down lithography etching process. Here, vertical Si hetero–structure Ge will be firstly fabricated first time demonstrate process, which applicable fabricate transistors. key step fabricating 3D construction insulating layer between contact electrodes. An isolation without chemical mechanical polishing steps was also developed control engineering at this length scale.