Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers

摘要: An embedded test pattern generator scheme for large-operand (unlimited bit length) multiplier and divider is presented by employing a simple digital circuit. This based on the generation of cyclic code polynomials from characterized G(X) incorporated with Modified-Booth algorithm. Due to advantages former, hardware complexity simple, moreover, can share same small change control lines. latter's schemes, numbers “sub/add” operations are reduced one half multiplicand result final product. Therefore, proposed pipelined multipliers permit very high throughput arbitrary value digit size. Only full adders/subtractors shift registers used in hardware. The input data multiplier/divider be processed parallel or without considering carry/borrow delays during operations. speed computation has therefore been greatly improved approximately factor 2. Since most parts components both divider, adders replaced subtractors switching structure tremendously reduced. In addition, these function units involved generators, so that they as built-in self-test (BIST).