Cell delay fault testing for iterative logic arrays

摘要: C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault occurs if and only an input transition can not be propagated to the cell's output through a path in specified clock period. The set of single-path propagation, hazard-free robust tests that completely check all paths is first derived, then necessary conditions sending this test each array simultaneously propagating effects primary outputs given. Test minimization solved similar way as cover problem. We use pipelined multiplier example, show it with 214 two-pattern tests. With small number additional patterns, combinational detected pseudoexhaustive.