An effective BIST architecture for sequential fault testing in array multipliers
作者： M. Psarakis , D. Gizopoulos , A. Paschalis , Y. Zorian
DOI: 10.1109/VTEST.1999.766673
关键词:
摘要: Sequential fault testing approaches for array multipliers proposed in the past target only external and impose significant hardware overhead due to excessive DFT modifications. In this paper we present, first time, a BIST architecture which does not require any modifications multiplier structure provides coverage larger than 99% comprehensive sequential model (RS-CFM) size. Both robust non-robust are considered. The applicability of is further justified considering case transistor stuck-open model, where also achieved case.
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