Robust and low-cost BIST architectures for sequential fault testing in datapath multipliers
作者： M. Psarakis , D. Gizopoulos , A. Paschalis , N. Kranitis , Y. Zorian
关键词:
摘要: The modified Booth array multiplier is the most ubiquitous architecture in datapaths of either general purpose microprocessors or specialized Digital Signal Processors. Sequential fault testing for multipliers has never been proposed past. In this paper, we present two BIST architectures with respect to Realistic Cell Fault model (RS-CFM). first aims resolve test invalidation problem largest possible extent, while second one cost reduction. Both achieve very high sequential coverage and impose moderate hardware delay overhead. Simplified variations are also presented non-recoded signed multipliers. Thus, offer a universal solution that covers totality multipliers: recoded.
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sci-hub.se 参考文章(16)
Gordon L. Smith, Model for Delay Faults Based Upon Paths international test conference. pp. 342- 351 ,(1985)
Gary L. Craig, Charles R. Kime, Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults. international test conference. pp. 126- 139 ,(1985)
Sandip Kundu, Niraj K. Jha, Testing and Reliable Design of CMOS Circuits ,(2011)
M.A. Gharaybeh, M.L. Bushnell, V.D. Agrawal, Classification and test generation for path-delay faults using single stuck-fault tests international test conference. pp. 139- 148 ,(1995) , 10.1109/TEST.1995.529827
M. Psarakis, D. Gizopoulos, A. Paschalis, Y. Zorian, An effective BIST architecture for sequential fault testing in array multipliers vlsi test symposium. pp. 252- 258 ,(1999) , 10.1109/VTEST.1999.766673
M.H. Woods, MOS VLSI reliability and yield trends Proceedings of the IEEE. ,vol. 74, pp. 1715- 1729 ,(1986) , 10.1109/PROC.1986.13687
Reddy, Reddy, Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits IEEE Transactions on Computers. ,vol. 35, pp. 742- 754 ,(1986) , 10.1109/TC.1986.1676825
R. L. Wadsack, Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits Bell System Technical Journal. ,vol. 57, pp. 1449- 1474 ,(1978) , 10.1002/J.1538-7305.1978.TB02106.X
Shyue-Kung Lu, Cheng-Wen Wu, Ruei-Zong Hwang, Cell delay fault testing for iterative logic arrays Journal of Electronic Testing. ,vol. 9, pp. 311- 316 ,(1996) , 10.1007/BF00134694
Chih-Yuang Su, Cheng-Wen Wu, Testing iterative logic arrays for sequential faults with a constant number of patterns IEEE Transactions on Computers. ,vol. 43, pp. 495- 501 ,(1994) , 10.1109/12.278489